1. Field of the Invention
The present invention generally relates to logic circuits, and, more particularly, to ratio logic circuits that increase the speed of a match bus operation in a superscalar microprocessor.
2. Description of the Related Art
Modem processors incorporating superscalar architecture allow a computer to execute multiple instructions out-of-order, but complete the instructions in program order to maintain program correctness. The architecture must be implemented within the constraints of a highly manufacturable die size and is implicitly required to operate at a high internal clock rate.
An instruction sequence with the "load" following the "store" in program order causes a load/store conflict in which the load instruction may have incorrect data. In these superscalar processors, the Load/Store Conflict (LSC) unit resolves problems created by out-of-order execution. The LSC compares memory dependencies (i.e., addresses) of instructions and flags any conflicts. These flags are then used to flush or discard the conflicting load instruction and all following instructions that have been dispatched.
Some have used standard CMOS (complementary metal-oxide semiconductor) logic cells such as NAND, NOR, XOR, and inverter gates to implement these operations. These bus operations, however, take about 3-4 gate delays (approximately 1000 pico-seconds (ps) in current technology) to implement. Unfortunately, these delay times are much to high for superscalar machines.
Other have tried bi-polar transistor designs, using TTL (transistor-transistor logic) or ECL (emitter-coupled logic) to increase bus speed. However, the bi-polar designs present heat, voltage, power, and compatibility problems with existing CMOS circuits.
In light of the foregoing, there exists a need for increasing the speed of the match bus operation to accommodate superscalar processor architecture, by minimizing the delay of compare and pattern detection operations on wide data width busses.